1. Field of the Invention
The invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a semiconductor device including an electrode composed of electrically conductive material and a capacity device comprised of a dielectric film, and a method of fabricating the same.
2. Description of the Related Art
There have been suggested so far various semiconductor devices including a capacity device. FIGS. 1A and 1B illustrate an example of such semiconductor devices. FIG. 1A is a plan view of one of conventional semiconductor devices, and FIG. 1B is a cross-sectional view taken along the line of IB--IB in FIG. 1A.
The illustrated semiconductor device is comprised of a semiconductor substrate 1, a first insulating layer 2 formed on the semiconductor substrate 1, a lower electrode 3 formed on the first insulating layer 2 and composed of first electrically conductive material, a dielectric film 4 formed on the lower electrode 3, an upper electrode 5 formed on the dielectric film 4 and composed of second electrically conductive material, a second insulating film 11 entirely covering the first insulating layer 2, the lower electrode 3, the dielectric film 4, and the upper electrode 5 therewith, a first wiring layer 8 making electrical contact with the lower electrode 3, and a second wiring layer 9 making electrical contact with the upper electrode 5.
The lower electrode 3 makes electrical contact with the first wiring layer 8 through a first contact hole 6 formed throughout the second insulating film 11, and the upper electrode 5 makes electrical contact with the second wiring layer 9 through a second contact hole 7 formed throughout the second insulating film 11.
The lower and upper electrodes 3 and 5 are composed of polysilicon films containing impurities such as arsenic and boron at about 1.times.10.sup.20 cm.sup.-3 and having a thickness in the range of about 150 to 300 nm. The lower and upper electrodes 3 and 5 have a sheet resistance in the range of 50 to 100 .OMEGA. per a unit area.
If the dielectric film 4 is composed of a silicon dioxide film having a thickness in the range of about 10 to 40 nm, and the upper electrode 5 is formed in a 20 .mu.m.times.20 .mu.m square, an area over which the lower and upper electrodes 3 and 5 overlap each other is 400 .mu.m.sup.2, and a capacity provided by the lower and upper electrodes 3 and 5 is in the range of about 0.3 to 1.2 pF.
The lower and upper electrodes 3 and 5 may be constituted of a film composed of tungsten silicide which is a compound of tungsten (W) and silicon (Si).
The semiconductor device having the above-mentioned structure has a capacity defined by an area over which the dielectric film 4, the lower electrode 3 and the upper electrode 5 overlap one another.
As the semiconductor device operates at a higher frequency, parasitic resistance of the lower and upper electrodes 3 and 5 would influence operation of the semiconductor device to a greater degree, resulting in that a capacity of the semiconductor device is varied due to a frequency.
Hence, it is quite important for a semiconductor device to reduce parasitic resistance of the lower and upper electrodes 3 and 5 in order to enhance performance of the semiconductor device.
A parasitic resistance of the upper electrode 5 is reduced generally as follows.
The second wiring layer 9 and the second contact hole 7 may be formed on the second insulating film 11, unless they are located above the upper electrode 5. Hence, as illustrated in FIG. 1A, it is possible to reduce a parasitic resistance of the upper electrode 5 by forming a plurality of the second contact holes 7 above the upper electrode 5, and electrically connecting the upper electrode 5 to the second wiring layer 9 through the second contact holes 7.
On the other hand, the lower electrode 3 is made in electrical contact with the first wiring layer 8.
As is obvious in view of FIG. 1B, it is not possible to form the first contact hole 6 between the first wiring layer 8 and the lower electrode 3 at a location where the upper electrode 5 exists. Hence, the first contact hole 6 is formed only outside the upper electrode 5.
When a parasitic resistance of the lower electrode 3 exerts only a small influence on the operation of a semiconductor device, a plurality of the first contact holes 6 are formed in a line outside and along a side of the upper electrode 5, as illustrated in FIG. 1A.
There have been suggested various structures for reducing a parasitic resistance of the lower electrode 5. For instance, one of such structures is suggested in Japanese Unexamined Patent Publication No. 59-47755.
FIGS. 2A, 2B and 2C illustrate a semiconductor device suggested in the above-mentioned Publication. FIG. 2A is a plan view of the semiconductor device, FIG. 2B is a cross-sectional view taken along the line IIB--IIB in FIG. 2A, and FIG. 2C is a cross-sectional view taken along the line IIIB--IIIB in FIG. 2C.
As illustrated in FIGS. 2B and 2C, the semiconductor device is comprised of a semiconductor substrate 11, a first insulating layer 12 formed on the semiconductor substrate 11, a lower electrode 13 formed on the first insulating layer 12 and composed of first electrically conductive material, a dielectric film 14 formed on the lower electrode 13, an upper electrode 15 formed on the dielectric film 14 and composed of second electrically conductive material, a second insulating film 21 entirely covering the first insulating layer 12, the lower electrode 13, the dielectric film 14, and the upper electrode 15 therewith, a first wiring layer 18 making electrical contact with the lower electrode 13, and a second wiring layer 19 making electrical contact with the upper electrode 15.
The lower electrode 13 makes electrical contact with the first wiring layer 18 through a first contact hole 16 formed throughout the second insulating film 21, and the upper electrode 15 makes electrical contact with the second wiring layer 19 through a second contact hole 17 formed throughout the second insulating film 21.
As illustrated in FIG. 2A, the lower electrode 13 is formed to extend outwardly from the upper electrode 15 at three sides, and the first wiring layer 18 is formed to have two extensions 18a extending in parallel with the second wiring layer 19. As a result, the first wiring layer 18 having the two extensions 18a surround the second wiring layer 19 at three sides thereof The first contact holes 16 are formed also between the lower electrode 13 and the extensions 18a.
Thus, the first contact holes 16 are positioned along three sides of the second wiring layer 19. The lower electrode 13 outwardly extends from the upper electrode 15 by a length of 3 .mu.m indicated as W2 along the three sides of the second wiring layer 19, and by a length of 1 .mu.m indicated as W3 along a remaining side of the second wiring layer 19.
If it is supposed that the upper electrode 15 is a 20 .mu.m.times.20 .mu.m square, a dimension of a capacity is determined in accordance with a dimension of the lower electrode 13. In the semiconductor device illustrated in FIGS. 2A to 2C, the capacity is a rectangle having a longer side which is 26 .mu.m long and a shorter side which is 24 .mu.m long, and hence, has an area of 624 .mu.m.sup.2. An area over which the lower and upper electrodes 13 and 15 overlap each other is 400 .mu.m.sup.2, and the capacity would be in the range of abut 0.3 to 1.2 pF.
If an area over which the lower and upper electrodes 13 and 15 overlap each other is made larger with the area being kept to be a square or a rectangle having a longer side and a shorter side almost equal in length to the longer side, a parasitic resistance would be significantly increased. In such a case, the lower electrode has to be formed to be a rectangle having a great ratio in length between longer and shorter sides, even though an area of the lower electrode is kept unchanged. This results in restriction in determination of a shape of the capacity.
As mentioned so far, a conventional capacity is accompanied with a problem that it is quite difficult to reduce a parasitic resistance of a lower electrode, which is hindrance to operation of a semiconductor device at high frequency.
In particular, an area over which lower and upper electrodes overlap each other has to be formed large for obtaining a high capacity. As a result, a length between the first contact hole 6 and a center of a capacity cannot avoid being long, which will cause problems that the lower electrode 3 is unavoidable to be large in size, and a parasitic resistance thereof is also unavoidable to be high.
In order to reduce a parasitic resistance of the lower electrode, there may be arranged a plurality of capacities each having a small capacitive value, to thereby construct a capacity having a desired high capacitive value. However, a resultant capacity cannot avoid being large in an area, resulting in that a semiconductor device including such a capacity cannot avoid being large in size.
For instance, Japanese Unexamined Patent Publication 5-55459 has suggested a semiconductor integrated circuit device including a plurality of octagonal lower electrodes. However, it is necessary to carry out the greater number of steps in order to form an octagonal lower electrode than the number of steps of a method of forming a square or rectangular electrode.